2024년 2월 25일 일요일

IMPI to Redfish

  • IPMI (Intelligent Platform Management Interface)
  • Redfish

Intel BMC 에서 MCTP over PCIe VDM 통신 경로 분석

2024년 2월 17일 토요일

BMC chipset

출처: ASPEED - AST2600

AST2600





AST2600 is ASPEED's 7th generation Server Management Processor, and also the world's first BMC SoC adopting 28nm advanced process technology. Adopting the Dual-core ARM Cortex A7 processor, AST2600 can optimize the performance and computing power; also lower the power consumption significantly. Also, AST2600 support Secure Boot mode and ARM Cortex A7 TrustZone, which can provide customers excellent information security protection.


Embedded CPU
  • Dual-core ARM Cortex A7
  • Embedded ARM Cortex M3
SDRAM Memory
  • DDR4 SDRAM with speed grade higher than DDR4-1600Mbps
  • Up to 2G Byte
  • ECC option
Flash MemorySPI flash memory SPI flash memory
Video-Over-IP
  • Video Redirection up to 1920x1200
  • YUV444/YUV420 Video Compression
  • 24 bits video compression quality
USB-Over-IP
  • USB 2.0 virtual hub controller with 5 devices supported
  • USB 1.1 HID device controller
BMC
  • BMC controller with IPMI 2.0/1.5 compliant
  • Remote Presence (iKVM)
  • PCIe host capability
  • eSPI/LPC
  • MCTP over PCIe
  • I2C/I3C/SMBus (Total 16 sets)
  • Virtual UART (1 set)
  • UART (13 sets and 1 set for FW debug)
  • GPIO (244 sets)
  • SGPIO (80 bits)
  • PWM (16 sets)
  • Secure boot engine
  • Fan tachometer (16 sets)
  • PECI 4.0
  • USB1.1/2.0 Host
  • SD/SDIO (2 ports)
  • Embedded SRAM
  • ADC (16 channels) Port 80h snoop
  • Watchdog (3 sets)
  • Timer (8 sets)
VGA
  • PCIe VGA/2D Controller
  • 1920x1200@60Hz 32bpp
VGA Drivers
  • RHEL
  • SLES
  • Solaris
  • Ubuntu
  • FreeBSD
  • Fedora
  • Windows Server 2012 R2 (WHQL logo'ed)
  • Windows Server 2016 (WHQL logo'ed)
  • Windows Server 2019 (WHQL logo'ed)
LANQuad 10/100/1000M bps MAC
Technology624-pin 21mmx21mm TFBGA package
Pin CompatibilityAST2620

2023년 9월 22일 금요일

Android kernel source code

  • Google Android kernel source (official)
    • https://android.googlesource.com/kernel/common/
      • git clone https://android.googlesource.com/kernel/common
    • kernel code update
      • git reset --hard HEAD
      • git pull
    • show current branch
      • git branch
    • git branch transition
      • git checkout <branch-name>
    • update code to up-to-date code
      • git pull
    • show log
      • git log
      • git log --author <name>
    • delete a local branch
      • git branch -d <branch-name>

2023년 5월 7일 일요일

ARM Custom Instructions and memory access

https://developer.arm.com/documentation/102900/0100/?lang=en


Arm Custom Instructions have some deliberate restrictions to help avoid implementation issues:

  1. They cannot directly access memory or inputs/outputs outside the processor.
  2. They cannot have their own register states.


Both restrictions above are necessary for enforcing security since the Arm architecture has clear definitions for secure accesses. If the Arm Custom Instruction were to define their own state (by having their own registers) or their own path to memory, the architecture can no longer claim to enforce security. An interrupt that forces a transition between Secure and Non-secure modes of execution could possibly lead to leaking of secure state from the custom execution logic block. For hardware accelerators that need internal state or direct memory access, the existing coprocessor interface feature can be a suitable solution.