ARMv7-M (Cortex-M3, M7) exception entry behavior

When pushing context to the stack, the hardware saves eight 32-bits words, comprising xPSR, Return Address, LR (R14), R12, R3, R2, R1 and R0.

Stack frame size = 8 x 32-bits = 32 bytes = 0x20 bytes

SP_main = SP_main - frame size;
frameptr = SP_main;

MemA[frameptr,4] = R[0];
MemA[frameptr+0x4,4] = R[1];
MemA[frameptr+0x8,4] = R[2];
MemA[frameptr+0xC,4] = R[3];
MemA[frameptr+0x10,4] = R[12];
MemA[frameptr+0x14,4] = LR;
MemA[frameptr+0x18,4] = ReturnAddress; /* Address of this instruction or next instruction depending on exception type and attribute */
MemA[frameptr+0x1C,4] = (XPSR<31:10>:frameptralign:XPSR<8:0>);

* Reference : "ARMv7-M Architecture Reference Manual B1.5.6 Exception entry behavior"

ARMv7-M (Cortex-M3, M7) CPU registers

• General registers : R0 ~ R12
• Stack Pointer register : R13 (SP, banked to SP_main(MSP), SP_process(PSP))
• Link Register : R14 (LR)
• Program Counter : R15 (PC)
• (Program) Status registers (flags, execution state, exception number) : xPSR
• Mask registers (priority of exception and interrupt)
• Control register (CONTROL, current stack mode, current Thread mode privilege level)

    All other registers are memory-mapped.

* Reference : "ARMv7-M Architecture Reference Manual B1.4 Registers"