ARMv7-M (Cortex-M3, M7) exception entry behavior

When pushing context to the stack, the hardware saves eight 32-bits words, comprising xPSR, Return Address, LR (R14), R12, R3, R2, R1 and R0.

Stack frame size = 8 x 32-bits = 32 bytes = 0x20 bytes

SP_main = SP_main - frame size;
frameptr = SP_main;

MemA[frameptr,4] = R[0];
MemA[frameptr+0x4,4] = R[1];
MemA[frameptr+0x8,4] = R[2];
MemA[frameptr+0xC,4] = R[3];
MemA[frameptr+0x10,4] = R[12];
MemA[frameptr+0x14,4] = LR;
MemA[frameptr+0x18,4] = ReturnAddress; /* Address of this instruction or next instruction depending on exception type and attribute */
MemA[frameptr+0x1C,4] = (XPSR<31:10>:frameptralign:XPSR<8:0>);

* Reference : "ARMv7-M Architecture Reference Manual B1.5.6 Exception entry behavior"

ARMv7-M (Cortex-M3, M7) CPU registers

• General registers : R0 ~ R12
• Stack Pointer register : R13 (SP, banked to SP_main(MSP), SP_process(PSP))
• Link Register : R14 (LR)
• Program Counter : R15 (PC)
• (Program) Status registers (flags, execution state, exception number) : xPSR
• Mask registers (priority of exception and interrupt)
• Control register (CONTROL, current stack mode, current Thread mode privilege level)

    All other registers are memory-mapped.

* Reference : "ARMv7-M Architecture Reference Manual B1.4 Registers"

SAMBA crash problem at Ubutntu 14.04.1

Look at this !!!

https://answers.launchpad.net/ubuntu/+question/291448

$ sudo apt-get install samba
$ sudo apt-get install --reinstall libsmbclient libsmbclient-dev libtevent0 libtalloc2

JTAG attaching when Cortex-M3 CPU is in sleep state by execution of WFI instruction

When Cortex-M3 CPU is in sleep state by execution of WFI instruction, is it possible to attach JTAG to M3?

1. Debug Halt from debugger can wake up CPU from WFI.
   https://developer.arm.com/docs/103489919/latest/how-can-a-cortex-m-processor-wake-up-from-wfi-if-interrupts-are-masked-or-disabled
   http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka16222.html
2. A Debug Entry request can wake up CPU from WFI.
   http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/BABFEFIG.html

Cortex-M3 WFI instruction and wake up by IRQ

[Question] If WFI instruction is executed in ISR of Cortex-M3 CPU, is it possible to wake up from it by arising of new IRQ?

[Answer] Yes if the priority of new IRQ is higher than current IRQ.
            But, I will confirm it by testing in Cortex-M3 CPU.

References:

• https://community.arm.com/processors/f/discussions/6930/race-condition-between-wake-up-event-and-wfi-on-cortex-m3-m4

RISC-V

http://blog.naver.com/v_lovepooh_v/221256905181

Core Dump Format

This is about how to make a core dump binary.

1. Q&A
• https://stackoverflow.com/questions/5986366/elf-core-file-format
2. Useful links
• http://www.gabriel.urdhr.fr/2015/05/29/core-file/
• http://uhlo.blogspot.com/2012/05/brief-look-into-core-dumps.html