OMAP4460

< OMAP4460 정리 >
                                                               2012-10-31 전용규

1. Chipset 정보

   ARM Cortex-A9 Processor
   (ARMv7-A Cortex)
 
 
2. MLO

   File name of the first stage boot loader in the first FAT32 partition of MMC
   = header + x-loader binary
 

3. Memory Subsystem

   = DMM + TILER + EMIF + GPMC + ELM + OCM + DMM

   X) GPMC
 
      : General-Purpose Memory Controller
      : for interfacing external memory devices;
        - Async SRAM-like memory
        - Async, sync, page mode burst NOR flash
        - NAND flash
        - Pseudo-SRAM devices
 
   X) OCM
 
      OCM (On-Chip Memory) subsystem consists of
      - on-chip ROM (SAR ROM) controller
      - on-chip RAM (SAR RAM) controller
      - on-chip SRAM (L3 SRAM) controller
   
      SAR ROM
      - 4-KB ROM, 32-bit access / cycle
   
      SAR RAM
      - 8-KB size
      - content in SAR RAM is preserved when the device goes into off mode
        as long as the wake-up voltage domain remains supplied.
      - Used as context-saving memory to be written by software so that
        sDMA restores its saved content when the device transitions from off to on mode.
      - 32-bit access / cycle
   
      L3 SRAM (= L3 OCM_RAM)
      - 56-KB RAM
      - Fully pipelined, 32-bit access / cycle
 
   X) SAR
 
      : Save-And-Restore
      : Hardware context saving for power saving.